1. Field of the Invention
The present invention relates to an input/output buffer, and more particularly, the invention relates to an input/output buffer protection circuit.
2. Description of the Related Art
Conventionally, most IC devices are driven by a system voltage in the range of 0–5 V (volt). In these IC devices, the high-voltage logic signal is therefore set at the system voltage and the low-voltage logic signal is set at the ground voltage. With advances in semiconductor technology, however, the system voltage can be now reduced to 3.3 V because the gate oxide layers in the IC device can be made thinner. Still lower system voltage may be possible in the future. In practice, however, a new 3.3 V IC device is typically used in conjunction with older 5 V peripheral devices. For example, a new 3.3 V VGA (video graphic adapter) IC may be used in conjunction with older 5 V peripheral devices in a personal computer, resulting in incompatibilities therebetween.
FIG. 1 is a schematic circuit diagram showing the circuit structure of a conventional I/O buffer used in a 3.3 V source voltage Vcc. As shown, the I/O buffer 10 is coupled to an input buffer 11 and an I/O pad 20 of an IC device. The I/O buffer 10 is composed of a PMOS transistor P1, and an NMOS transistor N1. When the I/O buffer operates in input mode, both the PMOS transistor P1 and the NMOS transistor N1 must be switched off. subjecting the PMOS transistor a high-voltage signal from the gate of PMOS transistor P1, for example 3.3 V, and the NMOS transistor to be subjected to the gate of the NMOS N1 Low-voltage signal, thereby switching the PMOS P1 and NMOS n1 into a non-conducting state.
If, however, the I/O pad 20 receives a 5 V input logic signal, the PMOS transistor P1 is subjected to a gate voltage of 3.3 V, a drain voltage of 5 V, and a source voltage of 3.3 V. Since the drain of the PMOS transistor P1 is connected to the I/O pad 20, which is now receiving the 5 V input logic signal which is higher than the 3.3 V system voltage, and the substrate thereof is connected to the 3.3 V system voltage, the PN junction diode will be subjected to a forward bias, thus causing an undesired leakage current to flow between the external 5 V source and the internal 3.3 V source.
As a solution to the aforementioned problem, an improved I/O buffer for the 3.3V IC has been proposed. FIG. 2 is a schematic diagram showing the improved I/O buffer. The I/O buffer further comprises an n-well circuit 3 and a gate control circuit 4, wherein the n-well circuit 3 includes a PMOS P2, PMOS P3, PMOS P4 and NMOS N4, the gate control circuit 4 includes a PMOS P5, a PMOS P6 and a NMOS N2. When the I/O buffer operates in input mode with a 5V input logic signal, the PMOS P2 and PMOS P3 of the n-well circuit 3 are turned on, thereby raising the potential of the n-well of PMOS P1 to 5V through PMOS P2. concurrently, the PMOS P4 is turned off and the PMOS P5 is turned on, raising the potential at the output of the gate control circuit 4 to 5V and is transfered to the gate of the PMOS P1.
When, however, a 5V signal is applied to the I/O pad 20, it causes the gate of the PMOS transistor P6 to receive the I/O signal through PMOS P3 and the potential is raised to 5V. When the voltage at the I/O pad 20 pulled down from high voltage (5V) to low voltage (0V), the PMOS P3 is switched off at about 3.3V, while the voltage at the gate terminal of the PMOS is still 3.3V. Thus, performance of the PMOS P6 may suffer.